1. Field of the Invention
The present invention relates to a package, particularly to a three-dimension (3D) integrated circuit (IC) package for system level ESD (Electrostatic Discharge) protection.
2. Description of the Related Art
Because the IC device sizes have been shrunk to nanometer scale, the consumer electronics, like the laptop and mobile devices, have been designed to be much smaller than ever. Without suitable protection devices, the functions of these electronics could be reset or even damaged under ESD (Electrostatic Discharge) events. Currently, all consumer electronics are expected to pass the ESD test requirement of IEC 61000-4-2 standard. TVS (Transient Voltage Suppressor) is generally designed to bypass the ESD energy, so that the electronic systems can be prevented from ESD damages.
The working principle of TVS is shown in FIG. 1. In FIG. 1, the TVS devices 10 are connected in parallel with the protected circuits 12 on the PCB (Printed Circuit Board). These TVS devices 10 would be triggered immediately when the ESD event is occurred. In that way, each TVS device 10 can provide a superiorly low resistance path for discharging the transient ESD current, so that the energy of the ESD transient current can be bypassed by the TVS devices 10.
FIG. 2 is a diagram showing a traditional two-dimension (2D) System-in-Package (SiP) with TVS. The SiP comprises a functional chip 14 and a TVS chip 16 installed on a die paddle 18. The functional chip 14 and the TVS chip 16 are connected with leads 20 by wire bonding. L1 and L2 are parasitic inductance of bond wire in traditional 2D package. If L1<L2, the impedance (ωL) of the ESD current path through the TVS chip 16 will be larger than that of the functional chip 14. The functional chip 14 will be damaged by ESD current before TVS chip 16 turned-on during system level ESD stress. Therefore, the ESD protection design in functional chip 14 is still necessary. Besides, a TVS is integrated in an IC chip in the traditional technology. When a breakdown voltage or input parasitic capacitance of the TVS requires to be changed, the complex fabrication process for IC is also changed, which increases the fabrication cost and may degrade performance for functional chip.
To overcome the abovementioned problems, the present invention provides a three-dimension (3D) integrated circuit (IC) package, so as to solve the afore-mentioned problems of the prior art.